Processing platforms such a microprocessor units, MPUs, microcontroller units, MCUs, and system-on-chips, SoCs, require random access memory for operating. In various operation stages, the random access memory used for storing data and instructions during normal operation of the processing platform is not available. Such operation stages include for instance production and functional testing, device initialization, safe mode operation and the like. Thus, sophisticated algorithms requiring random access memory may not be executable during those exemplary operation stages of the platform. Another option is for the random access memory to be too small for certain user applications and enhancements limiting the longevity of the processing platform.
For allowing complex algorithm to be processed during the initialization stage of a processing platform, Cache-as-RAM, CAR, techniques have been developed. The Cache-as-RAM or No-Eviction Mode (NEM) enables the use of e.g. a second level, L2, cache as random access memory. Cache-as-RAM is for instance applied during memory initialization stage of a processing platform initialization. In particular, the memory initialization stage of complex processing platforms such as system-on-chips can be a time consuming process. Using Cache-as-RAM techniques allows implementing sophisticated boot algorithms, which are already carried out before and during the memory initialization stage. However, Cache-as-RAM requires complex modifications on the logical level of the processing platforms, not applicable when there is a need for the L2 cache or when there is no L2 cache at all.
The present application provides a processing device enabled for use of idle storage capacity.